(1) Field of the Invention
The present invention generally relates to thermal management of semiconductor devices. More particularly, this invention relates to a heat-conductive structure capable of conducting and dissipating heat from a semiconductor device that requires electrical connections to its backside (topside) and frontside (e.g., circuit-side) surfaces.
(2) Description of the Related Art
Semiconductor devices exist that require electrical connections to opposite sides of the device as well as thermal management through the use of a heat sink placed in thermal contact with the device. Devices with these requirements are typically power semiconductor devices, including field effect transistors (FET's), insulated gate bipolar transistors (IGBT's), and power flip chips. These devices are typically enclosed in semiconductor packages in which the device is mounted to a copper slug and overmolded. The overmolded package is then mounted to a substrate by either through-hole or surface-mount soldering processes. In order to decrease circuit board area and product cost, there is a desire in the electronics industry to “depackage” these devices. One such approach is to mount the bare chip directly to a substrate (direct chip attach, or DCA) with its active circuit side (frontside) facing away from the substrate to which the device is mounted, and then wire bonding the frontside of the chip to bond pads on the surrounding substrate.
A difficulty encountered with overmold-packaged and DCA wire-bonded power semiconductor devices is the inability to adequately heat sink from the topside of the device (the “topside” being the surface of the device facing away from the substrate). Topside heat sinking requires a low thermal resistance path that is electrically isolated from the circuitry on the device surface. One such method is disclosed in commonly-assigned U.S. Pat. Nos. 6,180,436 and 6,365,964 to Koors et al., and involves conducting heat from a power flip chip with a heat-conductive pedestal brought into thermal contact with the topside of the chip, i.e., the surface opposite the solder connections that attach the chip to its substrate. However, such an approach is not compatible with power devices requiring electrical connections to both the front and topsides of the chip. Packaged devices electrically isolate the topside circuitry, but the epoxy used for encapsulation has high thermal resistance. For DCA devices, the wire bonds interfere with the placement of a topside heat sink, and copper straps often used as the heat sink are not electrically isolated from the circuitry.
There are several additional disadvantages to using wire bonding to make the electrical connection from a power semiconductor device to the substrate on which it is mounted. Since these devices drive high current loads, they may require multiple wire bonds. However, as the number of wire bonds increases, device yield can drop to unacceptable levels. Considering that many applications have numerous FET's or IGBT's, the total system yield can be reduced further. In the particular case of FET and IGBT devices, the active circuit under the wire bond sites can be damaged during the bonding process, generating additional yield losses. Furthermore, the use of multiple wire bonds may yield higher then desired current densities at the bond sites, causing regional heating. From a process perspective, the wire bond process itself is expensive due to the equipment requirements and the serial nature of the process. Finally, the number of wire bonds required for an FET device is becoming a major driver for sizing such devices because of the amount of chip area needed to bond out the device. This issue becomes more of a problem as silicon technology improvements increase the power density capability, which drives smaller die sizes.
From the above, it can be seen that current approaches to thermal management of power devices have drawbacks that limit their application and/or effectiveness, particularly in the case of DCA wire-bonded devices.